Significant research efforts are being focused on ultra-low power (ULP), small form factor mobile devices for applications such as health monitoring and the internet of things (IoT). These applications seek to extend battery life and/or achieve energy autonomy through energy harvesting and ULP design. Reducing the supply voltage (VDD) of digital circuits, typically near or below Vth, is an effective way to save power. An architectural technique to further optimize power consumption is to dynamically scale the supply voltage (DVS) based on workload. However, DVS varies gate delays exponentially below Vth, requiring dynamic frequency scaling in order to account for performance variations caused by voltage scaling. Therefore, there's a growing need for low-voltage, stable, programmable at run-time ULP clock generators (CKGEN). A number of sub-μW programmable clock generator solutions have already been reported, but they all lack programmability and therefore cannot offer dynamic frequency scaling. Current programmable clock generators are targeted towards high frequency and are too high power for NTC SoCs. A popular solution for clock programmability in microcontrollers is to generate the highest desired frequency with a crystal oscillator and then a divider generates lower frequencies. However, this is not a low-power solution, and cannot achieve the best possible performance as the phase noise degrades proportional to N2, where N is the divider ratio. Finally, IoT applications demand low-cost solutions, which for IC design translates to small form factor, case of integration and test, and minimal off-chip components. For these reasons, all-digital architectures leveraging the digital design flow are highly desirable. In this disclosure, a 187.5 kHz to 500 kHz ADPLL-based clock generators is presented that consumes 300 nW from a 0.5V VDD, has a jitter <0.1% and was implemented in a 0.13 μm process. The entire ADPLL was completely implemented using standard digital design flows and automatic place and route (APR). Moreover, an integrated crystal oscillator (31.25 kHz) is included and serves as the reference frequency for the PLL. Therefore, this is a complete programmable clock generator solution for ULP NTC platforms.
This section provides background information related to the present disclosure which is not necessarily prior art.